Developer Dashboard & Reference Hub
Part: XC7A100T-2FGG484I (Industrial Grade)
| FPGA Chip | XC7A100T-2FGG484I |
|---|---|
| Logic Cells | 101,440 |
| System Clock | 200MHz (Diff: R4/T4) |
| GTP Clock | 125MHz (Diff: F6/E6) |
| Memory | 1GB DDR3 (MT41J256M16HA) |
| Storage | 128Mbit QSPI (N25Q128) |
| PCIe / ETH | Gen2 x4 / Dual 1Gbps |
| HDMI I/O | SiI9013(IN) / SiI9134(OUT) |
WARNING
Power Sequencing
+1.0V (Core) → +1.8V (Aux) → +1.5V (DDR3) → +3.3V (IO)## System Clock (200MHz Differential) - Bank 34 set_property PACKAGE_PIN R4 [get_ports sys_clk_p] set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p] set_property PACKAGE_PIN T4 [get_ports sys_clk_n] set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n] create_clock -period 5.000 -name sys_clk_p -waveform {0.000 2.500} [get_ports sys_clk_p] ## Reset Button (T6) - Bank 34 set_property PACKAGE_PIN T6 [get_ports rst_n] set_property IOSTANDARD SSTL15 [get_ports rst_n] ## User LEDs (Active Low) set_property PACKAGE_PIN B13 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN C13 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN D14 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN D15 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] ## User Keys set_property PACKAGE_PIN J21 [get_ports key1] set_property IOSTANDARD LVCMOS33 [get_ports key1] set_property PACKAGE_PIN E13 [get_ports key2] set_property IOSTANDARD LVCMOS33 [get_ports key2] ## USB UART set_property PACKAGE_PIN P20 [get_ports uart_rxd] set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd] set_property PACKAGE_PIN N15 [get_ports uart_txd] set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity top_led_blink is Port ( sys_clk_p : in STD_LOGIC; sys_clk_n : in STD_LOGIC; rst_n : in STD_LOGIC; led : out STD_LOGIC_VECTOR (3 downto 0) ); end top_led_blink; architecture Behavioral of top_led_blink is signal clk_200m : STD_LOGIC; signal timer : STD_LOGIC_VECTOR(31 downto 0) := (others => '0'); signal led_reg : STD_LOGIC_VECTOR(3 downto 0) := "1110"; begin -- Differential Clock Buffer IBUFGDS_inst : IBUFGDS port map (O => clk_200m, I => sys_clk_p, IB => sys_clk_n); process(clk_200m, rst_n) begin if rst_n = '0' then timer <= (others => '0'); led_reg <= "1110"; elsif rising_edge(clk_200m) then if timer = 100000000 then -- 0.5 sec at 200MHz timer <= (others => '0'); led_reg <= led_reg(2 downto 0) & led_reg(3); else timer <= timer + 1; end if; end if; end process; led <= led_reg; end Behavioral;