VHDL IP CORE LIBRARY

> Synthesizable RTL Modules & Simulation Testbenches

UART_Transceiver.vhdl
tb_uart_transceiver.vhdl
-- UART Transmitter Logic library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity UART_TX is Port ( clk : in STD_LOGIC; tx_data : in STD_LOGIC_VECTOR(7 downto 0); tx_out : out STD_LOGIC ); end UART_TX; architecture Behavioral of UART_TX is type state_type is (IDLE, START, DATA, STOP); signal state : state_type := IDLE; begin -- Main Process process(clk) begin if rising_edge(clk) then case state is when IDLE => tx_out <= '1'; if tx_start = '1' then state <= START; end if; when START => tx_out <= '0'; state <= DATA; when DATA => tx_out <= tx_shift(0); when STOP => tx_out <= '1'; state <= IDLE; end case; end if; end process; end Behavioral;
-- UART Testbench library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tb_uart is end tb_uart; architecture sim of tb_uart is signal clk : std_logic := '0'; signal tx_out : std_logic; begin uut: entity work.UART_TX port map (clk => clk, tx_out => tx_out); clk_process: process begin clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process; stim_proc: process begin wait for 100 ns; -- Insert Stimulus here wait; end process; end sim;
Module Stats
Status Verified
FamilyArtix-7
Resource45 / 63400
Bus/Signal Activity
AXI4_Lite_Slave.vhdl
tb_axi4_lite_slave.vhdl
-- AXI4-Lite Slave Interface library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity AXI_Slave is Port ( S_AXI_ACLK : in STD_LOGIC; S_AXI_AWADDR : in STD_LOGIC_VECTOR(31 downto 0); S_AXI_WDATA : in STD_LOGIC_VECTOR(31 downto 0); S_AXI_WVALID : in STD_LOGIC ); end AXI_Slave; architecture Arch of AXI_Slave is signal reg0, reg1 : std_logic_vector(31 downto 0); begin process(S_AXI_ACLK) begin if rising_edge(S_AXI_ACLK) then if (S_AXI_WVALID = '1') then reg0 <= S_AXI_WDATA; end if; end if; end process; end Arch;
-- AXI4-Lite Bus Simulation -- Verifying Read/Write Handshake library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tb_axi is end tb_axi; architecture sim of tb_axi is signal aclk : std_logic := '0'; begin -- Bus Functional Model (BFM) Logic master_proc: process begin wait for 20 ns; -- Write Transaction awvalid <= '1'; wdata <= x"DEADBEEF"; wait until awready = '1'; wait; end process; end sim;
Module Stats
Status Verified
FamilyZynq-7000
Resource120 / 85000
Bus/Signal Activity
SPI_Master_Controller.vhdl
tb_spi_master_controller.vhdl
-- SPI Master Controller library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity SPI_Master is Port ( sclk : out STD_LOGIC; mosi : out STD_LOGIC; miso : in STD_LOGIC ); end SPI_Master; architecture rtl of SPI_Master is type state_t is (IDLE, TRANSFER); begin -- SPI Clock Generation process(sys_clk) begin if rising_edge(sys_clk) then -- Shift Register Logic if state = TRANSFER then mosi <= shift_reg(7); shift_reg <= shift_reg(6 downto 0) & miso; end if; end if; end process; end rtl;
-- SPI Loopback Testbench stim_proc: process begin wait for 50 ns; start_transfer <= '1'; data_in <= x"A5"; wait for 200 us; assert(rx_data = x"A5") report "Loopback Failed" severity error; end process;
Module Stats
Status Stable
FamilySpartan-6
Resource85 / 14000
Bus/Signal Activity
I2C_Master_Interface.vhdl
tb_i2c_master_interface.vhdl
-- I2C Master Logic -- Implements Start, Stop, Ack conditions process(clk) begin case state is when START => sda <= '0'; scl <= '1'; when WRITE_DATA => sda <= data_byte(bit_cnt); when READ_ACK => sda <= 'Z'; -- Release line if sda_in = '0' then ack <= '1'; end if; end case; end process;
-- I2C EEPROM Simulation -- Simulates reading/writing to 24LCxx Series process begin -- Send Start Condition wait for 10 us; -- Send Device Address (0xA0) -- Wait for Ack wait; end process;
Module Stats
Status Beta
FamilyArtix-7
Resource150 / 63400
Bus/Signal Activity
FIR_Filter_16tap.vhdl
tb_fir_filter_16tap.vhdl
-- High Performance FIR Filter -- Pipeline depth: 4 entity FIR_Filter is Port ( sample_in : in signed(15 downto 0); sample_out : out signed(31 downto 0) ); end FIR_Filter; architecture dsp of FIR_Filter is -- MAC (Multiply-Accumulate) Array begin process(clk) begin if rising_edge(clk) then acc <= (coeff(0) * tap(0)) + (coeff(1) * tap(1)); end if; end process; end dsp;
-- FIR Filter Impulse Response Test process begin -- Apply Impulse (1, 0, 0, 0...) sample_in <= x"7FFF"; -- Max positive wait for clk_period; sample_in <= (others => '0'); wait for 100 * clk_period; -- Check Output coefficients end process;
Module Stats
Status Optimized
FamilyKintex-7
ResourceDSP: 16
Bus/Signal Activity
PWM_Generator_Multi.vhdl
tb_pwm_generator_multi.vhdl
-- PWM Generator process(clk) begin if rising_edge(clk) then if counter < period then counter <= counter + 1; else counter <= 0; end if; if counter < duty_cycle then pwm_out <= '1'; else pwm_out <= '0'; end if; end if; end process;
-- PWM Duty Cycle Verification process begin duty_cycle <= 50; -- 50% wait for 1 ms; duty_cycle <= 25; -- 25% wait for 1 ms; duty_cycle <= 75; -- 75% wait; end process;
Module Stats
Status Verified
FamilyCyclone V
Resource32 / 25000
Bus/Signal Activity
Sync_FIFO_Buffer.vhdl
tb_sync_fifo_buffer.vhdl
-- Synchronous FIFO entity FIFO is Port ( wr_en : in STD_LOGIC; rd_en : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR(7 downto 0); full : out STD_LOGIC; empty : out STD_LOGIC ); end FIFO; architecture rtl of FIFO is type ram_type is array (0 to 255) of std_logic_vector(7 downto 0); signal mem : ram_type; signal wr_ptr, rd_ptr : integer := 0; begin -- Circular Buffer Logic full <= '1' when (wr_ptr + 1 = rd_ptr) else '0'; end rtl;
-- FIFO Read/Write Test process begin -- Write 10 values for i in 1 to 10 loop wr_en <= '1'; data_in <= std_logic_vector(to_unsigned(i, 8)); wait for clk_period; end loop; wr_en <= '0'; -- Read 10 values for i in 1 to 10 loop rd_en <= '1'; wait for clk_period; end loop; wait; end process;
Module Stats
Status Stable
FamilyGeneric
Resource60 / 10000
Bus/Signal Activity